Part # ADSP AD2199x ADAnomaly ADList datasheet

Part Manufacturer: Analog Devices

Analog Devices

Part Description: ADSP-2191M Anaomaly List for Revision 0.1


Part Details:

a Digital Signal Processing Division ADSP-2199x Anomaly List for Revisions up to 0.0 Created, 21 September 2006 These anomalies represent the currently known differences between revisions of ADSP-2199x devices and the functionality specified in the ADSP-2199x data sheets and ADSP-2199x DSP Core and Peripherals Manuals. A revision number with the form "-x.x" is branded on all parts. The table below represents the known anomalies for all devices of the ADSP-2199x family. Changes from the last version of this document (1/11/2005): 1. Added anomalies from #5 to #12. Anomaly List: Description: 1. SPORT Active low, late frame sync failure 2. DMA Write with Pipeline Stall 3. Peripheral DMA with EMI DMA Writes 4. Real time update of PWM period 5. SPORT generates TFS (Transmit Frame Sync) one clock cycle earlier than expected when configured for data-dependent and early frame sync mode 6. SPORT fails to check for the frame sync in unframed mode after it is disabled and re-enabled 7. RFS and TFS guard cycles after SPORT enable 8. Serial clock is not gated by SPORT enable bit 9. Changing the serial port clock frequency on the fly 10. Processor s PLL may not lock or work at frequencies lower than 40 MHz 11. SPORT Multichannel mode [TDM] bit shift and loss of channel 12. Emulation logic problem with DMA 1. SPORT Active low, late frame sync failure: When the SPORT is configured in active low, late frame sync mode, the data will not get framed (T/RFSx may not be asserted through out the data transfer) for both transmitting and receiving. Workaround: Do not use active low, late frame sync mode. Use active high, late frame sync mode with an external inverter on frame sync. NR003304A Page 1 of 8 a Digital Signal Processing Division 2. DMA Write with Pipeline Stall When a memDMA, ADC DMA or SPORT DMA is active, a DMA failure may occur if a pipeline stall coincides with DMA write activity. As a result, all DMA activity will be halted. Pipeline stalls could happen for the following reasons: a. Core IO read/writes (e.g. "AX0 = IO(0x300);") b. Direct Core accesses to EMI - especially for reads. The failure is independent of frequency. The SPI Port will not trigger this problem. Workaround: If DMA activity cannot be avoided, steps must be taken to ensure pipeline stalls due to accesses initiated by the core do not occur at the same time as the DMA transactions. · Do not perform I/O READ or WRITE transactions while memDMA , ADC DMA or SPORT is performing DMA WRITES to internal memory · Do not perform direct core external memory accesses while memDMA, ADC DMA or SPORT is performing DMA WRITES to internal memory Given that during Descriptor DMA the Core explicitly writes the ownership bit to give Ownership to the DMA peripheral, the core can monitor the Ownership bit (bit 15) in the DMA Configuration word in internal memory before doing any IO or external memory access. In other words, once the core hands over the DMA Ownership to the memDMA, ADC DMA or SPORT DMA, all further IO read/writes and external memory accesses should be restricted in software until the ownership is returned to the core (until DMA is completed). This means the core cannot do any IO accesses or external memory accesses when memDMA, ADC DMA or SPORT DMA is going on. It can still perform all the DSP computations and load/store from the internal memory. This workaround only applies to Descriptor based DMA. There is no workaround for Autobuffer DMA. 3. Peripheral DMA with EMI DMA Write When two or more instances of memDMA/ADCDMA/SPORT DMA are performing WRITES to internal memory and an external memory DMA WRITE access is initiated by any other peripheral DMA, all DMA transactions may halt. The anomaly only occurs when two or more instances of memDMA/ ADCDMA/SPORT DMA are performing WRITES to internal memory and a 3rd peripheral DMA attempts to perform a WRITE to external memory space. For example, the SPI could trigger the problem if they are performing DMA WRITES to external memory, and both memDMA and SPORT DMA are providing DMA WRITES to internal memory. Workaround: 1. Do not perform any external memory DMA WRITES while two or more instances of memDMA/ ADCDMA/SPORT DMA are performing WRITES to internal memory. NR003304A Page 2 of 8 a Digital Signal Processing Division 4. Real time update of PWM period When the PWM period is changed in real time (i.e. a new value is written in the register PWM0_TM), the first half of the new PWM period after the change is not as intended (please see figure below). After this first half, the following PWM periods have the right value. The anomaly happens in both single update and double update mode.


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