Part # AD808 datasheet

Part Manufacturer: Analog Devices

Analog Devices

Part Description: AD808 Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming

Part Details:

a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD808 FEATURES frequency acquisition without false lock. This eliminates a reli- Meets CCITT G.958 Requirements ance on external components such as a crystal or a SAW filter, for STM-4 Regenerator--Type A to aid frequency acquisition. Meets Bellcore TR-NWT-000253 Requirements for OC-12 The AD808 acquires frequency and phase lock on input data Output Jitter: 2.5 Degrees RMS using two control loops that work without requiring external 622 Mbps Clock Recovery and Data Retiming control. The frequency acquisition control loop initially acquires Accepts NRZ Data, No Preamble Required the frequency of the input data, acquiring frequency lock on Phase-Locked Loop Type Clock Recovery-- random or scrambled data without the need for a preamble. At No Crystal Required frequency lock, the frequency error is zero and the frequency Quantizer Sensitivity: 4 mV detector has no further effect. The phase acquisition control Level Detect Range: 10 mV to 40 mV, Programmable loop then works to ensure that the output phase tracks the input Single Supply Operation: +5 V or ­5.2 V phase. A patented phase detector has virtually eliminated pat- Low Power: 400 mW tern jitter throughout the AD808. 10 KH ECL/PECL Compatible OutputPackage: 16-Lead Narrow 150 mil SOIC The device VCO uses a ring oscillator architecture and patentedlow noise design techniques. Jitter is 2.5 degrees rms. This lowjitter results from using a fully differential signal architecture,Power Supply Rejection Ratio circuitry and a dielectrically PRODUCT DESCRIPTION isolated process that provides immunity from extraneous signals The AD808 provides the receiver functions of data quantiza- on the IC. The device can withstand hundreds of millivolts of tion, signal level detect, clock recovery and data retiming for power supply noise without an effect on jitter performance. 622 Mbps NRZ data. The device, together with a PIN The user sets the jitter peaking and acquisition time of the PLL diode/preamplifier combination, can be used for a highly inte- by choosing a damping factor capacitor whose value determines grated, low cost, low power SONET OC-12 or SDH STM-4 loop damping. CCITT G.958 Type A jitter transfer require- fiber optic receiver. ments can easily be met with a damping factor of 5 or greater. The receiver front end signal level detect circuit indicates when Device design guarantees that the clock output frequency will the input signal level has fallen below a user adjustable thresh- drift by less than 20% in the absence of input data transitions. old. The threshold is set with a single external resistor. The Shorting the damping factor capacitor, CD, brings the clock signal level detect circuit 3 dB optical hysteresis prevents chatter output frequency to the VCO center frequency. at the signal level detect output. The AD808 consumes 400 mW and operates from a single

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AD808.pdf Datasheet