Part # 74LS221 datasheet

Part Manufacturer: Motorola

Motorola

Part Description: 74LS221


Part Details:

SN54/74LS221 DUAL MONOSTABLEMULTIVIBRATORSWITH SCHMITT-TRIGGER INPUTS Each multivibrator of the LS221 features a negative-transition-triggered DUAL MONOSTABLE input and a positive-transition-triggered input either of which can be used as MULTIVIBRATORS an inhibit input. WITH SCHMITT-TRIGGER INPUTS Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows LOW POWER SCHOTTKY jitter-free triggering for inputs as slow as 1 volt / second, providing the circuitwith excellent noise immunity. A high immunity to VCC noise is also providedby internal latching circuitry. Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be J SUFFIX terminated by the overriding clear. Input pulse width may be of any duration CERAMIC relative to the output pulse width. Output pulse width may be varied from 35 CASE 620-09 nanoseconds to a maximum of 70 s by choosing appropriate timing 16 1 components. With Rext = 2.0 k and Cext = 0, a typical output pulse of 30nanoseconds is achieved. Output rise and fall times are independent of pulselength. Pulse width stability is achieved through internal compensation and is N SUFFIX virtually independent of VCC and temperature. In most applications, pulse PLASTIC stability will only be limited by the accuracy of external timing components. CASE 648-08 Jitter-free operation is maintained over the full temperature and V 16 CC ranges for greater than six decades of timing capacitance (10 pF to 10 µF), and 1 greater than one decade of timing resistance (2.0 to 70 k for theSN54LS221, and 2.0 to 100 k for the SN74LS221). Pulse width is definedby the relationship: t D SUFFIX w(out) = CextRext ln 2.0 0.7 Cext Rext; where tW is in ns if C SOIC ext is in pF and Rext is in k . If pulse cutoff is not critical, capacitance up 16 CASE 751B-03 to 1000 µF and resistance as low as 1.4 k may be used. The range of 1 jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature.· SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot ORDERING INFORMATION · Overriding Clear Terminates Output Pulse · SN54LSXXXJ Ceramic Pin Out is Identical to SN54 / 74LS123 SN74LSXXXN Plastic SN74LSXXXD SOIC


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74LS221.pdf Datasheet