Part # MAX9322 datasheet

Part Manufacturer: Maxim


Part Description: MAX9322 DS

Part Details:

19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322 General Description Features The MAX9322 low-skew 1:15 differential clock driver 1.2ps (RMS) Maximum Random Jitter reproduces or divides one of two differential input clocksat 15 differential outputs. An input multiplexer selects from 300mV Differential Output at 1.0GHz one of two input clocks with input switching frequency in 900ps Propagation Delay excess of 1.0GHz. The 15 outputs are arranged in fourbanks with 2, 3, 4, and 6 outputs, respectively. Each Selectable Divide-by-1 or Divide-by-2 Frequency output bank is individually programmable to provide a Outputs divide-by-1 or divide-by-2 frequency function. Multiplexed 2:1 Input Function The MAX9322 operates in LVPECL systems with a LVECL Operation from V +2.375V to +3.8V supply or in LVECL systems with a EE = -2.375V to -3.8V -2.375V to -3.8V supply. A VBB reference output pro- LVPECL Operation from VCC = +2.375V to +3.8V vides compatibility with single-ended clock input sig- nals and a master reset input provides a simultaneous ESD Protection: > 2kV Human Body Model reset on all outputs. The MAX9322 is available in 52-pin TQFP and 68-pin Ordering Information QFN packages and is specified for operation over-40°C to +85°C. For 1:10 clock drivers, refer to the PIN- MAX9311/MAX9313 data sheet. For 1:5 clock drivers, PART TEMP RANGE PACKAGE refer to the MAX9316 data sheet. MAX9322ECY -40°C to +85°C 52 TQFP Applications MAX9322ETK* -40°C to +85°C 68 QFN Precision Clock Distribution *Future product--contact factory for availability. Low-Jitter Data Repeaters Pin Configurations Central-Office Backplane Clock Distribution DSLAM Backplane TOP VIEW Base Stations VCCO QA0

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MAX9322.pdf Datasheet