Part # MAX9396 datasheet

Part Manufacturer: Maxim

Maxim

Part Description: MAX9396 DS


Part Details:

19-0736; Rev 0; 1/07 2:1 Multiplexer and 1:2 Demultiplexer with Loopback MAX9396 General Description Features The MAX9396 consists of a 2:1 multiplexer and a 1:2 Guaranteed 1.25Gbps Operation with 450mV (min) demultiplexer with loopback. The multiplexer section Differential Output Swing (channel B) accepts two differential inputs and gener-ates a single differential output. The demultiplexer sec- Integrated 100 Resistors on Differential Inputs tion (channel A) accepts a single differential input and Simultaneous Loopback Control generates two parallel differential outputs. TheMAX9396 features a loopback mode that connects the 2ps(RMS) (max) Random Jitter input of channel A to the output of channel B and con- AC Specifications Guaranteed for 150mV nects the selected input of channel B to the outputs of Differential Input channel A. The differential inputs of the MAX9396 accept Signal Inputs Accept Any Differential Signals with CML/LVPECL levels and can also accept LVDS inputs VCM = +0.6V to (VCC - 0.05V) with common-mode voltages from +0.6V to (VCC - LVDS Outputs for Clock or High-Speed Data 0.05V). The differential outputs are LVDS compatibleand drive 100 loads. Low-Level Input Fail-Safe Detection Three LVCMOS/LVTTL logic inputs control the internal +3.0V to +3.6V Supply Voltage Range connections between inputs and outputs, one for the LVCMOS/LVTTL Logic Inputs multiplexer portion of channel B (BSEL), and the othertwo for loopback control of channels A and B (LB_SELAand LB_SELB). Independent enable inputs for each dif-ferential output pair provide additional flexibility. Ordering Information Fail-safe circuitry forces the outputs to a differential low PIN- PKG condition for undriven inputs or when the common- PART TEMP RANGE PACKAGE CODE mode voltage is below +0.6V. MAX9396EHJ+ -40°C to +85°C 32 TQFP H32-1 Ultra-low 57psP-P (typ) pseudorandom bit sequence +Denotes a lead-free package. (PRBS) jitter ensures reliable communications in high-speed links that are highly sensitive to timing error,especially those incorporating clock-and-data recovery, Typical Operating Circuit or serializers and deserializers. The high-speed switch-ing performance guarantees 1.25Gbps operation and +3.0V TO


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MAX9396.pdf Datasheet