Part # 74LS256 datasheet

Part Manufacturer: Motorola


Part Description: 74LS256

Part Details:

SN54/74LS256 DUAL 4-BITADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and DUAL 4-BIT four outputs (Q0­Q3). ADDRESSABLE LATCH When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q LOW POWER SCHOTTKY 0 ­ Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output(Q0­Q3), determined by the Address inputs, follows D. When the E goesHIGH, the contents of the latch are stored. When operating in the addressablelatch mode (E = LOW, CL = HIGH), changing more than one bit of the Address(A0, A1) could impose a transient wrong address. Therefore, this should be J SUFFIX done only while in the memory mode (E = CL = HIGH). CERAMIC · Serial-to-Parallel Capability CASE 620-09 · 16 Output From Each Storage Bit Available 1 · Random (Addressable) Data Entry · Easily Expandable · Active Low Common Clear N SUFFIX · PLASTIC Input Clamp Diodes Limit High Speed Termination Effects CASE 648-08 16 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC CL E Db Q3b Q Q 2b 1b Q0b D SUFFIX 16 15 14 13 12 11 10 9 SOIC 16 CASE 751B-03 1

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74LS256.pdf Datasheet