Part # AT89S52 datasheet

Part Manufacturer: Atmel


Part Description: AT89S52

Part Details:

Features· Compatible with MCS®-51 Products· 8K Bytes of In-System Programmable (ISP) Flash Memory ­ Endurance: 10,000 Write/Erase Cycles · 4.0V to 5.5V Operating Range· Fully Static Operation: 0 Hz to 33 MHz· Three-level Program Memory Lock· 256 x 8-bit Internal RAM· 32 Programmable I/O Lines· Three 16-bit Timer/Counters 8-bit · Eight Interrupt Sources Microcontroller · Full Duplex UART Serial Channel· Low-power Idle and Power-down Modes with 8K Bytes · Interrupt Recovery from Power-down Mode· Watchdog Timer In-System · Dual Data Pointer· Power-off Flag Programmable · Fast Programming Time· Flexible ISP Programming (Byte and Page Mode) Flash · Green (Pb/Halide-free) Packaging Option 1. Description AT89S52 The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. 1919D­MICRO­6/08 2. Pin Configurations 2.1 40-lead PDIP 2.3 44-lead PLCC (T2) P1.0 1 40 VCC (T2 EX) P1.1 2 39 P0.0 (AD0) P1.2 3 38 P0.1 (AD1) P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P1.3 4 37 P0.2 (AD2)

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AT89S52.pdf Datasheet