Part # SPEAR-09-H122 datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics

Part Description: SPEArdatasheet Head600

Part Details:

SPEAR-09-H122 SPEArTM Head600 Preliminary Data Features ARM926EJ-S core @333 MHz 600 Kbyte reconfigurable logic array with 88 dedicated general purposes I/Os, 9 LVDS channels and 128 Kbyte configurable internal memory pool PBGA420 Multilayer AMBA 2.0 compliant bus with fMAX 166 MHz ­ 16 bpp DSTN panel 32 Kbyte ROM 10 GPIOs bidirectional signals with interrupt 8 Kbyte common static RAM capability Dynamic power saving features 88 RAS-GPIOs user customizable bidirectional High performance 8 channels DMA signals (up to 4 clocks) Ethernet 10/100/1000 MAC with GMII/MII ADC 10-bit, 1MSPS, 8 analog inputs interface to external PHY JPEG codec accelerator USB2.0 device with integrated PHY 10 independent timers with programmable 2 USB2.0 host with integrated PHY prescaler Ext. SDRAM memory interface: Real time clock ­ 8/16-bit ([email protected] MHz) WatchDog ­ 8/16-bit ([email protected] MHz) System controller Flashes interface: ­ Nand 8/16-bit MISC internal control registers ­ Serial (up to 50 Mbps) JTAG (IEEE1149.1) interface 3-SPI master/slave up to 40 Mbps Description I2C master/slave mode - high, fast and slow speed SPEAr Head600 is a powerful digital engine 2 independent UART up to 460.8 Kbps with belonging to SPEAr family, the innovative software flow control mode customizable system-on-chip. The device integrates an ARM 926 core with a IrDA (Fir-Mir-Sir) from 9.6 Kbps to 4 Mbps large set of proven IPs and a big configurable speed-rate logic block that allow very fast customization of Colour LCD controller: unique and/or proprietary solution. ­ up to 1024x768 resolutions The SPEAR-09-H122 is designed for the -40 to

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SPEAR-09-H122.pdf Datasheet