Part # SPEAR-09-H022 datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics

Part Description: SPEArdatasheet Head200 ARM 926, 200K customizable eASICdatasheet gates, large IP portfolio SoC


Part Details:

SPEAR-09-H022 SPEArTM Head200 ARM 926, 200K customizable eASICTM gates, large IP portfolio SoC Features ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces 200K customizable equivalent ASIC gates (16K LUT equivalent) with 8 channels internal DMA high speed accelerator function and 112 dedicated general purpose I/Os PBGA420 Multilayer AMBA 2.0 compliant bus with fMAX 133 MHz Programmable internal clock generator with ADC 8-bit, 230 Ksps, 16 analog input channels enhanced PLL function, specially optimized for Real-time clock E.M.I. reduction WatchDog 16 Kbyte single port SRAM embedded 4 general purpose timers Dynamic RAM interface: 16-bit DDR, 32 / 16-bit SDRAM Overview SPI interface connecting serial ROM and Flash devices SPEAr Head200 is a powerful digital enginebelonging to SPEAr family, the innovative 2 USB 2.0 host independent ports with customizable system-on-chip. integrated PHYs The device integrates an ARM core with a large USB 2.0 device with integrated PHY set of proven IPs (intellectual properties) and a Ethernet MAC 10/100 with MII management configurable logic block that allows very fast interface customization of unique and/or proprietary 3 independent UARTs up to 115 Kbps solutions, with low effort and low investment. (software flow control mode) Optimized for embedded applications. I2C master mode - fast and slow speed The SPEAR-09-H022 is designed for the -40 to 6 general purpose I/Os 85 °C ambient temperature range. Table 1. Device summary Order code Package Packing SPEAR-09-H022 PBGA420 (23x23x1.81 mm) Tray July 2008 Rev 6


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SPEAR-09-H022.pdf Datasheet