Part # 74F112 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: 74F112 Dual JK Negative Edge-Triggered Flip-Flop


Part Details:

74F1 April 1988 Revised September 2000 12 Dual 74F112 JK Negat Dual JK Negative Edge-Triggered Flip-Flop General Description Simultaneous LOW signals on SD and CD force both Q andQ HIGH. The 74F112 contains two independent, high-speed JK flip- iv flops with Direct Set and Clear inputs. Synchronous state Asynchronous Inputs: e LOW input to S Edge- changes are initiated by the falling edge of the clock. Trig- D sets Q to HIGH level gering occurs at a voltage level of the clock and is not LOW input to CD sets Q to LOW level directly related to the transition time. The J and K inputscan change when the clock is in either state without affect- Clear and Set are independent of clock T ing the flip-flop, provided that they are in the desired state Simultaneous LOW on CD and SD makes both Q ri during the recommended setup and hold times relative to and Q HIGH ggere the falling edge of the clock. A LOW signal on SD or CDprevents clocking and forces Q or Q HIGH, respectively. d Fl Ordering Code: ip- Order Number Package Number Package Description Flo 74F112SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow p 74F112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009472 www.fairchildsemi.com


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74F112.pdf Datasheet