Part # 74LS373 datasheet

Part Manufacturer: Motorola


Part Description: 74LS373

Part Details:

SN54/74LS373 OCTAL TRANSPARENT LATCH SN54/74LS374 WITH 3-STATE OUTPUTS;OCTAL D-TYPE FLIP-FLOPWITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus WITH 3-STATE OUTPUT organized system applications. The flip-flops appear transparent to the data(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW POWER SCHOTTKY LOW, the data that meets the setup times is latched. Data appears on the buswhen the Output Enable (OE) is LOW. When OE is HIGH the bus output is inthe high impedance state. The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea- turing separate D-type inputs for each flip-flop and 3-state outputs for bus ori- J SUFFIX ented applications. A buffered Clock (CP) and Output Enable (OE) is common CERAMIC to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low CASE 732-03 Power Schottky technology and is compatible with all Motorola TTL families. 20 · Eight Latches in a Single Package 1 · 3-State Outputs for Bus Interfacing · Hysteresis on Latch Enable N SUFFIX · Edge-Triggered D-Type Inputs PLASTIC · Buffered Positive Edge-Triggered Clock CASE 738-03 20 · Hysteresis on Clock Input to Improve Noise Margin 1 · Input Clamp Diodes Limit High Speed Termination Effects DW SUFFIX PIN NAMES LOADING (Note a) SOIC 20 HIGH LOW CASE 751D-03 1 D0 ­ D7 Data Inputs 0.5 U.L. 0.25 U.L. LE Latch Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L. CP Clock (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L.

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74LS373.pdf Datasheet