Part # 74ABT16500 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: 74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs


Part Details:

74AB April 1993 Revised January 1999 T16500 1 74ABT16500 8 18-Bit Universal Bus Transceivers with 3-STATE Outputs -Bit plementary (OEAB is active HIGH and OEBA is active General Description Univer LOW). The ABT16500 18-bit universal bus transceiver combines To ensure the high-impedance state during power up or D-type latches and D-type flip-flops to allow data flow in power down, OE should be tied to GND through a pulldownresistor; the minimum value of the resistor is determined by sal transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable the current-sourcing capability of the driver. Bus (OEAB and OEBA), latch-enable (LEAB and LEBA), andclock (CLKAB and CLKBA) inputs. For A-to-B data flow, the Features device operates in the transparent mode when LEAB is s Combines D-Type latches and D-Type flip-flops for T HIGH. When LEAB is LOW, the A data is latched if CLKAB operation in transparent, latched, or clocked mode ranscei is held at a HIGH or LOW logic level. If LEAB is LOW, the A s Flow-through architecture optimizes PCB layout bus data is stored in the latch/flip-flop on the HIGH-to-LOW s Guaranteed latch-up protection transition of CLKAB. Output-enable OEAB is active-high. s High impedance glitch free bus loading during entire When OEAB is HIGH, the outputs are active. When OEAB ver power up and power down cycle is LOW, the outputs are in the high-impedance state. s Non-destructive hot insertion capability s wi Data flow for B to A is similar to that of A to B but usesOEBA, LEBA, and CLKBA. The output enables are com- th 3-ST Ordering Code: Order Number Package Number Package Description AT 74ABT16500CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide E Out 74ABT16500CMTD MTD56


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74ABT16500.pdf Datasheet