Part # LM2502 datasheet

Part Manufacturer: National Semiconductor

National Semiconductor

Part Description: LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer

Part Details:

LM2502 January 2006 Mobile LM2502Mobile Pixel Link (MPL) Display Interface Serializer andDeserializer Pixel General Description Features The LM2502 device is a dual link display interface SERDES n >300 Mbps Dual Link Raw Throughput Link that adapts existing CPU / video busses to a low power n MPL Physical Layer (MPL-0) current-mode serial MPL link. The chipset may also be used n Pin selectable Master / Slave mode for a RGB565 application with glue logic. The interconnect is n Frequency Reference Transport reduced from 22 signals to only 3 active signals with the (MPL) n Complete LVCMOS / MPL Translation LM2502 chipset easing flex interconnect design, size and n Interface Modes: cost. -- 16-bit CPU, i80 or m68 style The Master Serializer (SER) resides beside an application -- RGB565 with glue logic processor or baseband processor and translates a parallel Display n -30°C to 85°C Operating Range bus from LVCMOS levels to serial MPL levels for transmis- n Link power down mode reduces I < 10 µA sion over a flex cable and PCB traces to the Slave Deseri- DDZ alizer (DES) located near the display module. n Dual Display Support (CS1* & CS2*) n Via-less MPL interconnect feature Dual display support is provided for a primary and sub and V ) display through the use of two ChipSelect signals. A Mode n 3.0V Supply Voltage (VDD DDA Interface pin selects either a i80 or m68 style interface. n Interfaces to 1.7V to 3.3V Logic (V ) DDIO The Power_Down (PD*) input controls the power state of theMPL interface. When PD* is asserted, the MD1/0 and MC System Benefits signals are powered down to save current. n Small Interface The LM2502 implements the physical layer of the MPL Stan- n Low Power dard (MPL-0). The LM2502 is offered in NOPB (Lead-free) n Low EMI

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LM2502.pdf Datasheet