Part # Application Note Communications T datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics


Part Details:

AN576 APPLICATION NOTE PCB LAYOUT OPTIMISATION INTRODUCTION Protection requirements are becoming more and more well known and are often defined by rules or stan-dards. To satisfy these requirements, there is, in the majority of cases, a standard solution or a dedicatedproduct. However, knowledge of the disturbances and the use of suitable protection devices are not sufficient inthemselves to solve the problem. In many applications, the correct design of the PCB layout is essentialfor success. Figure 1. Classical protection circuit Track B Track A I DEVICE TO BE DISTURBANCE PROTECTED SOURCE V P CL INFLUENCE OF THE PROTECTION LOCATION The circuit presented in Figure 1 shows the classical approach for the protection location. Here the pro-tection device (see Note 1) is located close to the module to be protected. When a disturbance occurs onthe track A the TRANSIL P clamps the surge at a maximum voltage VCL and thus protects the sensitivepart. During this clamping action there is a current through P and also in the track A. This phenomenon inducesa voltage on track B, where it is close to A. To avoid this undesirable parasitic overvoltage on track B, thecircuit of Figure 2 is recommended. Note: 1. TRANSIL devices are used as examples throughout this document, but the same arguments are valid for TRISILS. REV. 2A - 3588 May 2004 1/6 AN576 Figure 2. Recommended protection location Track B Track A I DEVICE TO BE PROTECTED VCL DISTURBANCE P SOURCE In this case the current due to the clamping phase of P remains located in the disturbance area and thetrack B is not affected. To summarize, it is recommended that the protection device is located as close as possible the distur-bance source. For example, all the lines coming into the board ought to be protected close to the connec-tor. INFLUENCE OF THE PCB LAYOUT ON THE ESD PROTECTION These days, printed circuit boards are often auto-routed by computer aided design and the track lengthsare not optimized. Figure 3. Non-optimized LAYOUT for ESD A P DEVICE TO BE U PROTECTED DISTURBANCE SOURCE B Figure 3 shows the classical non-optimized layout. When a surge occurs the protection device P acts andthere is a clamping voltage VCL across it. Due to the fast rise time of the ESD overvoltage there is a highdi/dt between the points A and B. This di/dt generates, in the parasitic inductances located between A andP and between B and P, overvoltages up to several hundred volts. So the applied voltage V across thedevice to be protected is the sum of the clamping voltage and the voltage across the parasitic inductance:thus the sensitive module is not protected. 2/6

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