Part # GTLP16617 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: GTLP16617 17-Bit TTL GTLP Synchronous Bus Transceiverwith Buffered Clock


Part Details:

GTLP166 June 1997 Revised December 2000 17 17- GTLP16617 Bit 17-Bit TTL/GTLP Synchronous Bus Transceiver T with Buffered Clock TL/GTLP General Description Features The GTLP16617 is a 17-bit registered synchronous bus s Bidirectional interface between GTLP and TTL logic transceiver that provides TTL to GTLP signal level transla- levels tion. It allows for transparent, latched and clocked modes s Designed with edge rate control circuitry to reduce S of data flow and provides a buffered GTLP (CLKOUT) output noise on the GTLP port y clock output from the TTL CLKAB. The device provides a nchronous s V high speed interface between cards operating at TTL logic REF pin provides external supply reference voltage for levels and a backplane operating at GTLP logic levels. receiver threshold adjustibility High speed backplane operation is a direct result of s Special PVT compensation circuitry to provide GTLP s reduced output swing (<1V), reduced input thresh- consistent performance over variations of process, old levels and output edge rate control. The edge rate con- supply voltage and temperature trol minimizes bus settling time. GTLP is a Fairchild s TTL compatible driver and control inputs Bus Semiconductor derivative of the Gunning Transceiver logic s Designed using Fairchild advanced CMOS technology (GTL) JEDEC standard JESD8-3. s Bushold data inputs on the A port eliminates the need Fairchild s GTLP has internal edge-rate control and is pro- for external pull-up resistors on unused inputs. T cess, voltage, and temperature (PVT) compensated. Its s Power up/down and power off high impedance for live r function is similar to BTL and GTL but with different output ansce insertion levels and receiver threshold. GTLP output LOW level istypically less than 0.5V, the output level HIGH is 1.5V and s 5 V tolerant inputs and outputs on the LVTTL port the receiver threshold is 1.0V. s Open drain on GTLP to support wired-or connection


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GTLP16617.pdf Datasheet