Part # 74LS90 datasheet

Part Manufacturer: Motorola

Motorola

Part Description: 74LS90


Part Details:

SN54/74LS90SN54/74LS92 DECADE COUNTER; SN54/74LS93 DIVIDE-BY-TWELVE COUNTER;4-BIT BINARY COUNTER DECADE COUNTER; The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed DIVIDE-BY-TWELVE COUNTER; 4-bit ripple type counters partitioned into two sections. Each counter has a di-vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or 4-BIT BINARY COUNTER divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi- LOW POWER SCHOTTKY tion on the clock inputs. Each section can be used separately or tied together(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All ofthe counters have a 2-input gated Master Reset (Clear), and the LS90 alsohas a 2-input gated Master Set (Preset 9).· Low Power Consumption . . . Typically 45 mW J SUFFIX · High Count Rates . . . Typically 42 MHz CERAMIC · Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, CASE 632-08 Binary 14 · 1 Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES LOADING (Note a) HIGH LOW N SUFFIX PLASTIC CP0 Clock (Active LOW going edge) Input to 0.5 U.L. 1.5 U.L. ÷ CASE 646-06 2 Section 14 CP1 Clock (Active LOW going edge) Input to 0.5 U.L. 2.0 U.L. 1 ÷5 Section (LS90), ÷6 Section (LS92) CP1 Clock (Active LOW going edge) Input to 0.5 U.L. 1.0 U.L. ÷8 Section (LS93) D SUFFIX MR1, MR2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L. SOIC 14 MS1, MS2


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74LS90.pdf Datasheet