Part # GTLP16T1655 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: GTLP16T1655 16-Bit LVTTL GTLP Universal Bus Transceiverwith High Drive GTLP and Individual Byte Controls


Part Details:

GTLP16T August 1998 Revised January 2005 1655 1 GTLP16T165516-Bit LVTTL/GTLP Universal Bus Transceiver 6-Bi with High Drive GTLP and Individual Byte Controls t LVTT General Description Features L/GTLP Uni The GTLP16T1655 is a 16-bit universal bus transceiver s Bidirectional interface between GTLP and LVTTL logic that provides LVTTL to GTLP signal level translation. It levels allows for transparent, latched and clocked modes of data s Variable edge rate control pin to select desired edge rate transfer. The device provides a high speed interface on the GTLP backplane (VERC) between cards operating at LVTTL logic levels and a back- s plane operating at GTLP logic levels. High speed back- VREF pin provides external supply reference voltage forreceiver threshold adjustibility ver plane operation is a direct result of GTLP s reduced outputswing (<1V), reduced input threshold levels and output s Special PVT compensation circuitry to provide consis- sal edge rate control. The edge rate control minimizes bus set- tent performance over variations of process, supply volt- tling time. GTLP is a Fairchild Semiconductor derivative of age and temperature the Gunning Transceiver Logic (GTL) JEDEC standard Bus T s TTL compatible driver and control inputs JESD8-3. s Designed using Fairchild advanced BiCMOS technology Fairchild s GTLP has internal edge-rate control and is pro- s Bushold data inputs on A port to eliminate the need for cess, voltage, and temperature (PVT) compensated. Its r external pull-up resistors for unused inputs anscei function is similar to BTL and GTL but with different outputlevels and receiver threshold. GTLP output LOW level is s Power up/down and power off high impedance for live typically less than 0.5V, the output level HIGH is 1.5V and insertion the receiver threshold is 1.0V. s Open drain on GTLP to support wired-or connection ver s Flow through pinout optimizes PCB layouts D-type flip-flop, latch and transparent data paths wit s A Port source/sink -24mA/+24mAs B Port sink +100mA h Hi s Partitioned as two 8-bit transceivers with individual latch timing and output control but with a common clock


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GTLP16T1655.pdf Datasheet