Part # Application Note Network STE10100 AN1350 datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics

Part Description: STE10 100A EEPROM ACCESS AND PROGRAMMING


Part Details:

AN1350 APPLICATION NOTE STE10/100A - EEPROM ACCESS AND PROGRAMMING 1.0 EEPROM There are four EEPROM interface pins (Can refer to "CSR9 SPR - Serial Port Register" on page 22/66 of the STE10/100A Data Sheet) s EEPROM data out, EDO (pin 72) s Serial ROM data in, EDI (pin 73) s Serial ROM clock, ECK (pin 74) s Serial ROM chip select, EECS (pin 76) The STE10/100A is designed to support serial interface to a 93C46 EEPROM. The EEPROM has three types of information: · Information that is used by the STE10/100A · Information that can be used by the STE10/100A driver· CIS data The information that is used by the STE10/100A is located in the ID block. These blocks are automati- cally read by the STE10/100A without software involvement. The ID block is read upon a hardware reset or when the STE10/100A transitions from the D3 power state to the D0 power state. The ID block is located at the top of the EEROM, beginning in address 0. The STE10/100A driver accesses the EEPROM through CSR9. The access sequences and timing are handled by the software. The EEPROM operations in this method can be read, write, or erase. The read and write operations in this method are described in the following sections. The erase operation is han-dled very similarly to the read and write operations. 2.0 Read Operation Obsolete Product(s) - Obsolete Product(s) Read operations consist of three phases: 1. Command phase--3 bits (binary code of 110) 2. Address phase--6 bits for 256-bit to 1 Kb ROMs, 8 bits for 2 Kb to 4 Kb ROMs. 3. Data phase--16 bits Figure 1 and Figure 2 show a typical read cycle that describes the action steps that need to be taken by the driver to execute a read cycle. The timing (listed on the right side of the figures) specifies the mini- mum time that the driver must wait before advancing to the next action. During both the address phase in Figure 1 and data phase in Figure 2, 1 bit is handled during each phase cycle. Therefore, the address February 2001 1/8 AN1350 APPLICATION NOTE phase should be repeated 6 or 8 times depending on the address length and data phase should be repeated 16 times. Note the value DX is the current data bit. Obsolete Product(s) - Obsolete Product(s) Figure 1. Read Cycle (1 of 2) 2/8 AN1350 APPLICATION NOTE Figure 2. Read Cycle (2 of 2) The read operation timing of the address and data are showed below: Obsolete Product(s) - Obsolete Product(s) Figure 3. Read Operation 3/8


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Application Note Network STE10100 AN1350.pdf Datasheet