Part # Application Note Public Telecom STLC60133 AN1591 datasheet 

Part Manufacturer: ST Microelectronics 

Part Description: STLC60133 SMALL SIGNAL SPICE MOD 

Part Details:AN1591 APPLICATION NOTE STLC60133 SMALL SIGNAL SPICE MODEL by Michele Fava, Stefano Garotta This document outlines the small signal SPICE model of the STLC60133 xDSL Line Driver, a dual amplifier featuring a large bandwidth optimized for XDSL applications. Information about model features and limits, indication on model utilization and test circuit schematicsare included. INTRODUCTION STLC60133 small signal SPICE model is a simulation model of the STLC60133 xDSL Line Driver for AC analysis.It is a simplified but accurate derivation of the complete Eldo® description of the circuit.xDSL systems performances heavily depend on Line Drivers features as distortion, noise and bandwidth. Distortion and noise are parameters very difficult to simulate with a simplified model, even using a full transistormodel results are very far from the precision needed by an xDSL system.The value of a model lies on its capability to simulate reality, and the need of a simplified model comes fromcomputing resources, these are the reasons why we focused our model only on small signal features.Those allow evaluating device compatibility with different application circuits (Line Interfaces) and main featuresof its AC behavior. Overall circuit performances should be verified with laboratory testing. Following sections describe model features, limits and performances. FEATURES STLC60133 small signal SPICE model is the small signal model of the STLC60133 xDSL line driver.It models one of the two amplifiers that compose the STLC60133.The model of the complete device is simply the union of two of these models, forming 4 inputs (IN1P, IN1N,IN2P, IN2N), 2 outputs (OUT1, OUT2) device.Active devices are modeled through their small signal models (hybrid model for transistors and small signalconductance for diodes), all components relevant parasitic resistance and capacitance has been taken into account.This model has been designed to run an AC analysis to evaluate STLC60133 performances when it is connected inside an application circuit, usually a line interface scheme.Testable characteristics are: Frequency response Input impedance Output impedance Open loop differential gain Stability These parameters are well modeled till frequencies above a few hundred MHz, than the effect of parasitic component begin more relevant and a direct laboratory testing is advised. September 2002 1/8 AN1591 APPLICATION NOTE LIMITSTo use the STLC60133 small signal SPICE model in a correct way, model limits have to be clearly kept in mind.They are mainly the ones of a small signal model, this means that characteristics such as distortion, slew rate,output dynamic, output current capability and variation with temperature can not be simulated.Neither can be run DC nor transient analysis. TEST CIRCUIT SCHEMATIC Circuit schematic used to test model performances versus complete STLC60133 Eldo® model, is described inthis section.It helps to understand and verify model features. Special interest feature of the model is the frequency response of the Line Driver in an Open Loop configuration.As specified in [1] SPICE techniques permit the use of particular methods to obtain accurate gain and phaseinformation for closedloop analog circuits that use negative feedback.More precisely, Open Loop Gain (OLG) can be evaluated by collecting the potential of the input nodes in a noninverting closed loop configuration.The OLG is then given by the ratio: V(inm)/(V(inp)V(inm)) (1) Looking at a tipycal loopback scheme: Figure 1. Loopback scheme inp out + G inm H It can be seen that inm = H * out (2) So H = inm / out (3) at the same time out = G * (inp  inm) (4) so G = out / (inp  inm) (5) the OLG is defined as the product OLG = G * H by joining relation (3) and (5) OLG = inm / (inp  inm) that is still relation (1)Test circuit schematic used for the evaluation of the OLG is shown in Figure 2.As specified in [2], for proper device operating it is necessary to work with a gain level greater than 6, i.e. 15.6dB. 2/8 AN1591 APPLICATION NOTE Figure 2. Open Loop Gain Test Circuit inp V1 X1 stlc60133 R1 1.2k 

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