Part # ADSP-218XN ADSERIES datasheet

Part Manufacturer: Analog Devices

Analog Devices

Part Description: ADSP-218xN DSP Microcomputer Final Data Sheet Revision A August 2006


Part Details:

a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES 12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus- Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation tained performance All inputs tolerate up to 3.6 V regardless of mode Single-cycle instruction execution 16-bit internal DMA port for high-speed access to on-chip Single-cycle context switch memory (mode selectable) 3-bus architecture allows dual operand fetches in every 4M-byte memory interface for storage of data tables and pro- instruction cycle gram overlays (mode selectable) Multifunction instructions 8-bit DMA to byte memory for transparent program and data Power-down mode featuring low CMOS standby power dissi- memory transfers (mode selectable) pation with 200 CLKIN cycle recovery from power-down Programmable memory strobe and separate I/O memory condition space permits "glueless" system design Low power dissipation in idle mode Programmable wait state generation INTEGRATION FEATURES Two double-buffered serial ports with companding hardware and automatic data buffering ADSP-2100 family code compatible (easy to use algebraic Automatic booting of on-chip program memory from byte- syntax), with instruction set extensions wide external memory, for example, EPROM, or through Up to 256K byte of on-chip RAM, configured internal DMA Port Up to 48K words program memory RAM Six external interrupts Up to 56K words data memory RAM 13 programmable flag pins provide flexible system signaling Dual-purpose program memory for both instruction and UART emulation through software SPORT reconfiguration data storage ICE-PortTM emulator interface supports debugging in final Independent ALU, multiplier/accumulator, and barrel shifter systems computational units Two independent data address generatorsPowerful program sequencer provides zero overhead loop- ing conditional instruction execution Programmable 16-bit interval timer with prescaler100-lead LQFP and 144-ball BGA P O W E R-D O W N C ONTR O L FU L L M EM O R Y M O D E M EM OR Y PRO GRA M


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ADSP-218XN ADSERIES.pdf Datasheet