Part # AD800 AD802 datasheet

Part Manufacturer: Analog Devices

Analog Devices

Part Description: AD800/AD802 Clock Recovery and Data Retiming Phase-Locked Loop

Part Details:

a Clock Recovery and Data Retiming Phase-Locked Loop AD800/AD802* FUNCTIONAL BLOCK DIAGRAM FEATURESStandard Products CD 44.736 Mbps--DS-351.84 Mbps--STS-1155.52 Mbps--STS-3 or STM-1 DATA COMPENSATING LOOP Ø ZERO INPUT DET FILTER Accepts NRZ Data, No Preamble RequiredRecovered Clock and Retimed Data Outputs VCO Phase-Locked Loop Type Clock Recovery--No Crystal RECOVERED Required CLOCK fDET OUTPUT Random Jitter: 20 Peak-to-PeakPattern Jitter: Virtually Eliminated RETIMED RETIMING DATA DEVICE 10KH ECL Compatible OUTPUT Single Supply Operation: ­5.2 V or +5 V AD800/AD802 FRAC Wide Operating Temperature Range: ­40 C to +85 C OUTPUT PRODUCT DESCRIPTION During the process of acquisition the frequency detector The AD800 and AD802 employ a second order phase-locked provides a Frequency Acquisition (FRAC) signal which loop architecture to perform clock recovery and data retiming indicates that the device has not yet locked onto the input data. on Non-Return to Zero, NRZ, data. This architecture is This signal is a series of pulses which occur at the points of cycle capable of supporting data rates between 20 Mbps and 160 slip between the input data and the synthesized clock signal. Mbps. The products described here have been defined to work Once the circuit has acquired frequency lock no pulses occur at with standard telecommunications bit rates. 45 Mbps DS-3 and the FRAC output. 52 Mbps STS-1 are supported by the AD800-45 and The inclusion of a precisely trimmed VCO in the device AD800-52 respectively. 155 Mbps STS-3 or STM-1 are eliminates the need for external components for setting center

Please click the following link to download the datasheet:

AD800 AD802.pdf Datasheet