Part # 74LS73 datasheet

Part Manufacturer: National Semiconductor

National Semiconductor

Part Description: DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Part Details:

Master-Slave DM54LS73ADM74LS73A June 1989 DM54LS73A DM74LS73A Dual Negative-Edge-TriggeredMaster-Slave J-K Flip-Flops with Clear J-K and Complementary Outputs Flip-Flops General DescriptionThis device contains two independent negative-edge-trig- and K inputs is allowed to change while the clock is high or gered J-K flip-flops with complementary outputs The J and low without affecting the outputs as long as setup and hold K data is processed by the flip-flops on the falling edge of times are not violated A low logic level on the clear input the clock pulse The clock triggering occurs at a voltage will reset the outputs regardless of the levels of the other Dual level and is not directly related to the transition time of the inputs negative going edge of the clock pulse The data on the J with Negative-Edge-Triggered Connection Diagram Clear Dual-In-Line Package and Complementary TL F 6372 ­ 1 Order Number DM54LS73AJ DM54LS73AW DM74LS73AM or DM74LS73AN Outputs See NS Package Number J14A M14A N14A or W14B Function Table Inputs Outputs CLR CLK J K Q Q L X X X L H H v L L Q0 Q0 H v H L

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74LS73.pdf Datasheet