Part # Application Notes Mobile Communications PD54003L-E DB-54003L-175 AN2657 datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics

Part Description: An innovative verilog model for predicting LDMOS DC, small and large signal behavior


Part Details:

AN2657 Application note An innovative verilog model for predicting LDMOS DC, small and large signal behavior Introduction To reduce the design cycle time and cost for wireless applications it is useful to have models that can help RF Engineers predict and simulate the behavior of RF power transistors. Recently, STMicroelectronics has been strongly focused on developing new models for RF LDMOS power transistors. The model introduced here is simple in concept, and describes with good approximation DC, small signal S-parameter and large signal behavior, and could be a starting point for designers in developing their new applications. This model has been implemented in Agilent Advanced Design System, in verilog Language, and includes the parasitic elements of the package, as well as a thermal node which takes self heating effects into account. In this applicatio note we will briefly describe how to extract the model parameters for the PD54003L-E device, which is a 3 W - 7.2 V - 500 MHz LDMOS housed in a PowerFLAT plastic package (5 x 5 mm). As an internally unmatched device, the PD54003L-E can be used in various portable applications over HF, VHF and UHF frequency bands. At the end of this note we will validate this new model using ST s DB-54003L-175 demoboard, especially designed for 2-way portable radio applications using PD54003L-E over the 135-175 MHz frequency band. Thanks to their cost effectiveness and high performance, LDMOS devices are widely used in radio frequency applications, ranging from digital communication infrastructures (cellular base stations) to low cost portable radios (private mobile radios) commonly known as walkie-talkies. November 2007 Rev 1 1/18 www.st.com Contents AN2657 Contents 1 Model description and parameter extraction . . . . . . . . . . . . . . . . . . . . . 4 2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 AN2657 List of figures List of figures Figure 1. Model schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Rjfet vs. Vds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Gate-drain charge variation vs. Vds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Generic internal RF package structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. PowerFLAT cross-section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Simulated version of the PowerFLAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. S-parameters of the simulated package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8. Overall model schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9. Measured Ciss, Coss, Crss vs. simulated parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10. Measured S-parameters vs. simulated parameters (Vds= 7.2 V; Idq= 100 mA) . . . . . . . . 14 Figure 11. Measured input and output DC curves vs. simulated curves . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12.


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