Part # ADSP ADTS201S datasheet

Part Manufacturer: Analog Devices

Analog Devices

Part Description: Data Sheet Final - ADSP-TS201 TigerSHARC Embedded Processor Rev. C


Part Details:

· a TigerSHARC® Embedded Processor ADSP-TS201S KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate Provides high performance static superscalar DSP 24M bits of internal--on-chip--DRAM memory operations, optimized for telecommunications 25 mm × 25 mm (576-ball) thermally enhanced ball grid infrastructure and other large, demanding multiprocessor array package DSP applications Dual-computation blocks--each containing an ALU, a Performs exceptionally well on DSP algorithm and I/O multiplier, a shifter, a register file, and a communications benchmarks (see benchmarks in Table 1) logic unit (CLU) Supports low overhead DMA transfers between internal Dual-integer ALUs, providing data addressing and pointer memory, external memory, memory-mapped peripherals, manipulation link ports, host processors, and other Integrated I/O includes 14-channel DMA controller, external (multiprocessor) DSPs port, four link ports, SDRAM controller, programmable Eases DSP programming through extremely flexible instruc- flag pins, two timers, and timer expired pin for system tion set and high-level-language-friendly DSP architecture integration Enables scalable multiprocessing systems with low commu- 1149.1 IEEE-compliant JTAG test access port for on-chip nications overhead emulation Provides on-chip arbitration for glueless multiprocessing Single-precision IEEE 32-bit and extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats JTAG PORT DATA ADDRESS GENERATION 24M BITS INTERNAL MEMORY SOC BUS 6 INTEGER 32 32 INTEGER MEMORY BLOCKS JTAG J ALU K ALU (PAGE CACHE) EXTERNAL PROGRAM


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ADSP ADTS201S.pdf Datasheet