Part # 74LCX573 datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics

Part Description: Octal D-type latch non-inverting (3-state) with 5V tolerant inputs and outputs


Part Details:

74LCX573 OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS s 5V TOLERANT INPUTS AND OUTPUTS s HIGH SPEED:tPD = 8.0 ns (MAX.) at VCC = 3V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE:|I SOP TSSOP OH| = IOL = 24mA (MIN) at VCC = 3V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: Table 1: Order Codes tPLH tPHL PACKAGE T & R s OPERATING VOLTAGE RANGE:VCC(OPR) = 2.0V to 3.6V (1.5V Data SOP 74LCX573MTR Retention) TSSOP 74LCX573TTR s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 enable input (LE) and an output enable input (OE). s LATCH-UP PERFORMANCE EXCEEDS While the LE inputs is held at a high level, the Q 500mA (JESD 17) outputs will follow the data input. When the LE is s ESD PERFORMANCE: taken low, the Q outputs will be latched at the logic HBM > 2000V (MIL STD 883 method 3015); level of D input data. While the (OE) input is low, MM > 200V the 8 outputs will be in a normal logic state (high orlow logic level) and while (OE) is in high level, the DESCRIPTION outputs will be in a high impedance state. The 74LCX573 is a low voltage CMOS OCTAL It has same speed performance at 3.3V than 5V D-TYPE LATCH with 3 STATE OUTPUT AC/ACT family, combined with a lower power NON-INVERTING fabricated with sub-micron consumption. silicon gate and double-layer metal wiring C2MOS All inputs and outputs are equipped with


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74LCX573.pdf Datasheet