Part # STSMIA832 datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics

Part Description: 1.8 V/2.8 V high speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer


Part Details:

STSMIA832 1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Feature summary s Sub-low voltage differential signaling inputs: VID = 100mV MIN. with RT = 100, CL = 10pF s High signaling rate:fIN = 650 Mbps MAX (D+,D-,STRB+,STRB-) fOUT = 82 MHz MAX (CLK) µTFBGA25 fOUT = 82 Mbps MAX (for each data line D1-D8) s Very high speed strobe to clock:tp Description LH~tpHL=5.2ns (TYP) at VDD=2.8V; VL=1.8V s Operating voltage range: The STSMIA832 receiver converts the subLVDS VDD(OPR) = 2.65V to 3.6V clock/datastream (up to 650 Mbps throughput V bandwidth) back into parallel 8 bits of L(OPR) =1.65V to 1.95V CMOS/LVTTL. The device recognizes the SMIA s Symmetrical output impedance (D1-D8, H- 32 bit start of frame (SOF), end of frame (EOF), SYNC, V-SYNC, CLK): start of line (SOL) and end of line (EOL) IIOHI=IOL=4mA (MIN) at VDD=2.65V;VL=1.8V sequences to generate the H-SYNC and V-SYNC s Low power dissipation (DISABLED: EN=Gnd): signals. Output LVTTL clock (up to 82 MHz) is I transmitted in parallel with data. Output data are SOFF = IDD + IL = 10 µA (Max) rising-edge strobes. This chipset is an ideal s SMIA specification compliant means to link mobile camera modules to s CLASS 0 and CLASS 1,2 supported (config by Baseband processors. In order to minimize static CLASS_SEL) current consumption, it is possible to shut down s CMOS logic input threshold the device when the interface is not being used by (EN, SYNC_SEL, CLASS_SEL): a power-down (EN) pin that reduces the V Maximum Current Consumption to 10 µA making IL = 0.3xVL; VL = 1.65V to 1.95V this device ideal for portable applications like VIH = 0.7xVL; VL = 1.65V to 1.95V


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STSMIA832.pdf Datasheet