Part # 74F109 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: 74F109 Dual JK Positive Edge-Triggered Flip-Flop

Part Details:

74F109 D April 1988 Revised September 2000 ual 74F109 JK Dual JK Positive Edge-Triggered Flip-Flop Posi General Description Asynchronous Inputs: ti LOW input to S The F109 consists of two high-speed, completely indepen- D sets Q to HIGH level ve Edge-T dent transition clocked JK flip-flops. The clocking operation LOW input to CD sets Q to LOW level is independent of rise and fall times of the clock waveform. Clear and Set are independent of clock The JK design allows operation as a D-type flip-flop (refer Simultaneous LOW on C to F74 data sheet) by connecting the J and K inputs. D and SD makes both Q and Q HIGH rigge red Fli p-Fl Ordering Code: op Order Number Package Number Package Description 74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009471 Truth Table 74F109 Inputs Outputs SD

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74F109.pdf Datasheet