Part # 54LS161A datasheet

Part Manufacturer: National Semiconductor

National Semiconductor

Part Description: 54LS161A DM54LS161A 54LS163A DM54LS163A Synchronous 4-Bit Binary Counters

Part Details:

4-Bit 54LS161ADM54LS161ADM74LS161A May 1992 Binary 54LS161A DM54LS161A DM74LS161A54LS163A DM54LS163A DM74LS163A Counters Synchronous 4-Bit Binary CountersGeneral DescriptionThese synchronous presettable counters feature an inter- gating Instrumental in accomplishing this function are two nal carry look-ahead for application in high-speed counting count-enable inputs and a ripple carry output designs The LS161A and LS163A are 4-bit binary counters Both count-enable inputs (P and T) must be high to count The carry output is decoded by means of a NOR gate thus and input T is fed forward to enable the ripple carry output preventing spikes during the normal counting mode of oper- The ripple carry output thus enabled will produce a high-lev- ation Synchronous operation is provided by having all flip- el output pulse with a duration approximately equal to the flops clocked simultaneously so that the outputs change co- high-level portion of the QA output This high-level overflow incident with each other when so instructed by the count- ripple carry pulse can be used to enable successive cascad- enable inputs and internal gating This mode of operation ed stages High-to-low level transitions at the enable P or T eliminates the output counting spikes which are normally inputs may occur regardless of the logic level of the clock associated with asynchronous (ripple clock) counters A These counters feature a fully independent clock circuit buffered clock input triggers the four flip-flops on the rising Changes made to control inputs (enable P or T or load) that (positive-going) edge of the clock input waveform will modify the operating mode have no effect until clocking These counters are fully programmable that is the outputs occurs The function of the counter (whether enabled dis- may be preset to either level As presetting is synchronous abled loading or counting) will be dictated solely by the setting up a low level at the load input disables the counter conditions meeting the stable set-up and hold times 54LS163ADM54LS163ADM74LS163A and causes the outputs to agree with the setup data afterthe next clock pulse regardless of the levels of the enable Features input The clear function for the LS161A is asynchronous Y Synchronously programmable and a low level at the clear input sets all four of the flip-flop Y outputs low regardless of the levels of clock load or en- Internal look-ahead for fast counting able inputs The clear function for the LS163A is synchro- Y Carry output for n-bit cascading nous and a low level at the clear inputs sets all four of the Y Synchronous counting flip-flop outputs low after the next clock pulse regardless of

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