Part # 74ALVC16500 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: 74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs


Part Details:

74AL October 2001 Revised October 2001 VC1650 74ALVC16500 0 Low V Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs olt General Description Features ag The ALVC16500 is an 18-bit universal bus transceiver s 1.65V­3.6V VCC supply operation e which combines D-type latches and D-type flip-flops to s 3.6V tolerant inputs and outputs 18- allow data flow in transparent, latched, and clocked modes. s t Data flow in each direction is controlled by output-enable PD (A to B, B to A) Bit (OEAB and OEBA), latch-enable (LEAB and LEBA), and 3.4 ns max for 3.0V to 3.6V VCC clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the 4.0 ns max for 2.3V to 2.7V V Uni CC device operates in the transparent mode when LEAB is 7.0 ns max for 1.65V to 1.95V V HIGH. When LEAB is LOW, the A data is latched if CLKAB CC ver is held at a HIGH or LOW logic level. If LEAB is LOW, the A s Power-off high impedance inputs and outputs bus data is stored in the latch/flip-flop on the HIGH-to-LOW s Supports live insertion/withdrawal (Note 1) sal Bus transition of CLKAB. When OEAB is HIGH, the outputs are s Uses patented noise/EMI reduction circuitry active. When OEAB is LOW, the outputs are in a high- s impedance state. Latchup conforms to JEDEC JED78 s Data flow for B to A is similar to that of A to B but uses ESD performance: Human body model > 2000V T OEBA, LEBA, and CLKBA. The output enables are com- r plementary (OEAB is active HIGH and OEBA is active Machine model >200V anscei


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