Part # 74VHC240 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: 74VHC240 Octal Buffer Line Driver with 3-STATE Outputs

Part Details:

74VHC240 Octal Buff April 2007 74VHC240 tm Octal Buffer/Line Driver with 3-STATE Outputs Features General Description er/Line Driver with 3-ST High Speed: tPD = 3.6ns (typ) at TA = 25°C The VHC240 is an advanced high speed CMOS octal Low power dissipation: I bus buffer fabricated with silicon gate CMOS technology. CC = 4µA (max) @ TA = 25°C High noise immunity: V It achieves high speed operation similar to equivalent NIH = VNIL = 28% VCC (min.) Bipolar Schottky TTL while maintaining the CMOS low Power down protection is provided on all inputs power dissipation. The VHC240 is an inverting 3-STATE Low noise: VOLP = 0.9V (max.) buffer having two active-LOW output enables. This Pin and function compatible with 74HC240 device is designed to drive buslines or buffer memoryaddress registers. An input protection circuit ensures that 0V to 7V can beapplied to the input pins without regard to the supplyvoltage. This device can be used to interface 5V to 3Vsystems and two supply systems such as battery ATE Outputs backup. This circuit prevents device destruction due tomismatched supply and input voltages. Ordering Information Package Order Number Number Package Description 74VHC240M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0­I7 Inputs O0­O7 Outputs 3-STATE Outputs ©1992 Fairchild Semiconductor Corporation

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74VHC240.pdf Datasheet