Part # GTLP18T612 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: GTLP18T612 18-Bit LVTTL GTLP Universal Bus Transceiver

Part Details:

GTLP18T May 1999 Revised July 2002 612 18 GTLP18T61218-Bit LVTTL/GTLP Universal Bus Transceiver -Bit General Description Features LV The GTLP18T612 is an 18-bit universal bus transceiver s Bidirectional interface between GTLP and LVTTL logic TTL/ which provides LVTTL to GTLP signal level translation. It levels allows for transparent, latched and clocked modes of data s Designed with edge rate control circuitry to reduce out- transfer. The device provides a high speed interface for GTLP Uni put noise on the GTLP port cards operating at LVTTL logic levels and a backplane s V operating at GTLP logic levels. High speed backplane REF pin provides external supply reference voltage for operation is a direct result of GTLP s reduced output swing receiver threshold adjustibility (< 1V), reduced input threshold levels and output edge rate s Special PVT compensation circuitry to provide consis- control. The edge rate control minimizes bus settling time. tent performance over variations of process, supply volt- GTLP is a Fairchild Semiconductor derivative of the Gun- age and temperature vers ning Transistor logic (GTL) JEDEC standard JESD8-3. s TTL compatible driver and control inputs Fairchild s GTLP has internal edge-rate control and is Pro- s Designed using Fairchild advanced BiCMOS technology a cess, Voltage, and Temperature (PVT) compensated. Its l s Bushold data inputs on A port to eliminate the need for Bus T function is similar to BTL or GTL but with different output external pull-up resistors for unused inputs levels and receiver thresholds. GTLP output LOW level is s Power up/down and power off high impedance for live less than 0.5V, the output HIGH is 1.5V and the receiver insertion threshold is 1.0V. r s Open drain on GTLP to support wired-or connection anscei s Flow through pinout optimizes PCB layouts D-type flip-flop, latch and transparent data pathss A Port source/sink -24mA/+24mA ver s B Port sink +50mAs Also packaged in plastic Fine-Pitch Ball Grid Array

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GTLP18T612.pdf Datasheet