Part # AD809 datasheet

Part Manufacturer: Analog Devices

Analog Devices

Part Description: AD809 155.52 MHz Frequency Synthesizer

Part Details:

a 155.52 MHz Frequency Synthesizer AD809 FEATURES 155.52 Mbps ports. The AD809 can be applied to create the trans- Frequency Synthesis to 155.52 MHz mit bit clock for one or more ports. 19.44 MHz or 9.72 MHz Input An input signal multiplexer supports loop-timed applications Reference Signal Select Mux where a 155.52 MHz transmit bit clock is recovered from the Single Supply Operation: +5 V or ­5.2 V 155.52 Mbps received data. Output Jitter: 2.0 Degrees RMSLow Power: 90 mW The low jitter VCO, low power and wide operating temperature 10 KH ECL/PECL Compatible Output range make the device suitable for generating a 155.52 MHz bit 10 KH ECL/PECL/TTL/CMOS Compatible Input clock for SONET/SDH/Fiber in the Loop systems. Package: 16-Pin Narrow 150 Mil SOIC The device has a low cost, on-chip VCO that locks to either8× or 16× the frequency at the 19.44 MHz or 9.72 MHz input.No external components are needed for frequency synthesis; how-ever, the user can adjust loop dynamics through selection of adamping factor capacitor whose value determines loop damping. PRODUCT DESCRIPTION The AD809 design guarantees that the clock output frequency The AD809 provides a 155.52 MHz ECL/PECL output clock from will drift low (by roughly 20%) in the absence of a signal at the either a 19.44 MHz or a 9.72 MHz TTL/CMOS/ECL/PECL refer- input. ence frequency. The AD809 functionality supports a distributedtiming architecture, allowing a backplane or PCB 19.44 MHz or The AD809 consumes 90 mW and operates from a single power 9.72 MHz timing reference signal to be distributed to multiple supply at either +5 V or ­5.2 V. FUNCTIONAL BLOCK DIAGRAM CF1 CF2 7 8 CLKIN (19.44MHz 13 AUTO LOOP OR PFD VCO SELECT FILTER 9.72MHz)CLKINN 12 BWADJUST TTL/CMOSIN 10 AUTO SELECT DIVIDE BY 8/16 AD809 PECLIN 2 5 CLKOUT MUX (155MHz)

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AD809.pdf Datasheet