Part # 54ACT112 datasheet

Part Manufacturer: National Semiconductor

National Semiconductor

Part Description: 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop


Part Details:

54ACT1 September 1998 12 54ACT112 Dual Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous Inputs: JK LOW input to S sets Q to HIGH level The ACT112 contains two independent, high-speed JK D Negative flip-flops with Direct Set and Clear inputs. Synchronous state LOW input to C sets Q to LOW level D changes are initiated by the falling edge of the clock. Trigger- Clear and Set are independent of clock ing occurs at a voltage level of the clock and is not directly Simultaneous LOW on C and S makes both Q and Q D D related to the transition time. The J and K inputs can change HIGH when the clock is in either state without affecting the flip-flop,provided that they are in the desired state during the recom-mended setup and hold times relative to the falling edge of Features Edge-T the clock. A LOW signal on S or C prevents clocking and D D n ACT112 has TTL-compatible inputs forces Q or Q HIGH, respectively. Simultaneous LOW sig- n Outputs source/sink 24 mA nals on S and C force both Q and Q HIGH. D D n Standard Microcircuit Drawing (SMD) 5962-8995001 riggered Connection Diagram Pin Descriptions Pin Names Description Pin Assigment for J , J , K , K Data Inputs DIP and Flatpack 1 2 1 2 CP , CP Clock Pulse Inputs 1 2 (Active Falling Edge)


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54ACT112.pdf Datasheet