Part # 74F377 datasheet

Part Manufacturer: Fairchild Semiconductor

Fairchild Semiconductor

Part Description: 74F377 Octal D-Type Flip-Flop with Clock Enable


Part Details:

74F377 April 1988 Revised September 2000 Octa 74F377 l D-T Octal D-Type Flip-Flop with Clock Enable ype General Description Features Fl The 74F377 has eight edge-triggered, D-type flip-flops with s Ideal for addressable register applications ip- individual D inputs and Q outputs. The common buffered s Clock enable for address and data synchronization Clock (CP) input loads all flip-flops simultaneously, when applications F the Clock Enable (CE) is LOW. lo s Eight edge-triggered D-type flip-flops The register is fully edge-triggered. The state of each D p wit s Buffered common clock input, one setup time before the LOW-to-HIGH clock transi-tion, is transferred to the corresponding flip-flop s Q output. s See 74F273 for master reset version The CE input must be stable only one setup time prior to s See 74F373 for transparent latch version h the LOW-to-HIGH clock transition for predictable operation. s See 74F374 for 3-STATE version Cl ock Ordering Code: Enable Order Number Package Number Package Description 74F377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" tot he ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009525


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