Part # 74GTL1655A datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics


Part Details:

74GTL1655A 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION s HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER:tPD = 4.6 ns (MAX.) A to B at VCC = 3V s COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN TRANSPARENT, LATCHED, OR CLOCKED MODE TSSOP s OPERATING VOLTAGE RANGE:VCC(OPR) = 3.0V to 3.6V Table 1: Order Codes s SYMMETRICAL OUTPUT IMPEDANCE:|IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT) PACKAGE T & R s OUTPUT IMPEDANCE:I TSSOP 74GTL1655ATTR OL = 100mA (MIN) at VCC = 3V (B PORT) s HIGH-IMPEDANCE STATE DURING POWER UP AND POWER DOWN up to Figure 1: Pin Connection VCC=BIASVCC=1.5V PERMITT LIVE INSERTION s B-PORT PRECHARGED BY BIASVCC REDUCE NOISE ON THE LINE DURING LIVE INSERTION s EDGE RATE-CONTROL INPUT CONFIGURES THE B-PORT OUTPUT RISE AND FALL TIMES s BUS HOLD ON DATA INPUTS ELIMINATES THE NEED FOR EXTERNAL PULL-UP/PULL-DOWN RESISTORS (A PORT) s DISTRIBUTED VCC AND GND PIN CONFIGURATION MINIMIZES HIGH-SPEED SWITCHING NOISE IN PARALLEL COMUNICATIONS s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 1655 DESCRIPTIONThe 74GTL1655A devices are 16-bit high-drive(100mA), low-output-impedance universal bustransceivers designed for backplane applications.The 74GTL1655A devices provide live-insertion Obsolete Product(s) - Obsolete Product(s) capability for backplane applications by toleratingactive signals on the data ports when the devicesare powered off. In addition, a biasing pinpreconditions the GTL/GTL+ port to minimizedisruption to an active backplane. The edge rate-control (VERC) input is provided so the rise and fall time of the B outputs can beconfigured to optimize for various backplaneloading conditions. Data flow in each direction is Rev. 1 October 2004 1/16 74GTL1655A controlled by output-enable (OEAB and OEBA), Active bus-hold circuitry is provided on the A port latch-enable (LEAB and LEBA), and clock (CLK) to hold unused or floating data inputs at a valid inputs. For A-to-B data flow, the devices operate logic level. When VCC is between 0 and 1.5 V, the in the transparent mode when LEAB is high. When

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74GTL1655A.pdf Datasheet