Part # TC74LVX74F FN FT datasheet

Part Manufacturer: Toshiba


Part Description: Dual D-Type Flip-Flop with Preset and Clear

Part Details:

TC74LVX74F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LVX74F,TC74LVX74FN,TC74LVX74FT Dual D-Type Flip-Flop with Preset and Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74LVX74F/ FN/ FT is a high-speed CMOS D-flip flop fabricated with silicon gate CMOS technology. Designed for use in TC74LVX74F 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. This device is suitable for low-voltage and battery operated systems. The signal level applied to the D input is transferred to Q output during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input low. An input protection circuit ensures that 0 to 5.5V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features · High-speed: fmax = 145 MHz (typ.) (VCC = 3.3 V) · Low power dissipation: I TC74LVX74FN CC = 2 A (max) (Ta = 25°C) · Input voltage level: VIL = 0.8 V (max) (VCC = 3 V) VIH = 2.0 V (min) (VCC = 3 V) · Power-down protection provided on all inputs · Balanced propagation delays: tpLH - tpHL · Pin and function compatible with 74HC74 TC74LVX74FT Weight SOP14-P-300-1.27A : 0.18 g (typ.) SOP14-P-300-1.27 : 0.18 g (typ.) SOL14-P-150-1.27 : 0.12 g (typ.) TSSOP14-P-0044-0.65A : 0.06 g (typ.) 1 2006-06-01 TC74LVX74F/FN/FT Pin Assignment (top view) IEC Logic Symbol (4) PR 1 S CLR 1 1

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TC74LVX74F FN FT.pdf Datasheet