Part # 245 datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics


Part Details:

® TA245 TECHNICAL ARTICLE The Code Shadowing Approach: Choose The Correct Non-Volatile Memory Yvon Bahout, EEPROM and Serial NVM Division, significantly shorter than those for NVM. The Application Lab Manager, access time of a standard parallel Flash is today STMicroelectronics, in the range of 50 ns, while that of a standard fast Rousset RAM is in the range of 10 ns, i.e. 5 times faster. Code Shadowing The speed of memory access tends to be the These access time considerations provide the limiting factor in determining processor perfor- rationale for the Code Shadowing strategy. Here mance (measured in millions of instructions per the executable code is stored in an NVM memory second, or MIPS) for any given application. (typically a Flash memory) and is downloaded intoRAM after each application power-up. The Master This article outlines the code shadowing strategy fetches thereafter instructions from RAM only. for optimising processor performance in systemswhere executable code is stored in Non-Volatile Bus Architectures Memory (NVM). Related design issues arediscussed, and in this context the M25Pxx serial Another significant factor in determining proces- Paged Flash from STMicroelectronics is sor performance is the bus architecture. Machine presented as an example. code instructions may consist of 1, 2, 3, or 4bytes, depending on an instruction s complexity. Access Time With an 8-bit bus, the Master must fetch instruc-tions byte by byte, whereas with a 32-bit bus the The time for a processor to fetch an instruction Master fetches an instruction word of 32 bits in a from memory is dependent on the memory s single shot. A 32-bit bus is therefore up to 4 times access time. This is the time for the memory to faster at fetching instructions than an 8-bit bus. output a word once its address has been receivedfrom the processor. For NVM, the level of a float- For an application using the code shadowing ing gate represents a binary digit in an analogue strategy, the bus width of the NVM can be manner, and comparing this level against a refer- reduced to a minimum, thus reducing manufactur- ence value is a time-consuming process. In ing costs. This slows only code downloading on contrast, binary values in RAM are available as power-up; processor performance while running logical states in a flip-flop, with the value stored as the application is determined by the RAM bus either 0 V or VCC. Here the state can be rapidly width. determined. Access times for RAM are therefore May 2002

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