Part # 74LS112 datasheet

Part Manufacturer: Motorola


Part Description: 74LS112

Part Details:

SN54/74LS112A DUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goesHIGH, the inputs are enabled and data will be accepted. The logic level of the DUAL JK NEGATIVE J and K inputs may be allowed to change when the clock pulse is HIGH and EDGE-TRIGGERED FLIP-FLOP the bistable will perform according to the truth table as long as minimum set-upand hold time are observed. Input data is transferred to the outputs on the LOW POWER SCHOTTKY negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 620-09 16 1 Q Q 5(9) 6(7) N SUFFIX PLASTIC CLEAR (CD) SET (SD) CASE 648-08 16 15(14) 4(10) J K 1 3(11) 2(12) 1(13) CLOCK (CP) D SUFFIX SOIC 16 CASE 751B-03 1 ORDERING INFORMATION SN54LSXXXJ Ceramic MODE SELECT -- TRUTH TABLE SN74LSXXXN Plastic SN74LSXXXD SOIC INPUTS OUTPUTS OPERATING OPERA MODE SD

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74LS112.pdf Datasheet