Part # Application Note General Purpose Products Accessories Adapters Audio Car Entertainment Computer Power Supply Corded Terminals Co datasheet

Part Manufacturer: ST Microelectronics

ST Microelectronics

Part Description: What happens to the M24xxx I²C EEPROM if the I²C bus communication is stopped?


Part Details:

AN1471 Application note What happens to the M24xxx I²C EEPROM if the I²C bus communication is stopped? This Application note describes what can be attempted to set an M24xxx memory back to a known state if it has been suddenly stopped before completion of the current I²C instruction. The method presented here will work regardless of whether the device was stopped during an incoming or an outgoing Byte transfer. It is used to resynchronize the memory device whenever an undefined state has been detected on the I²C bus. 1 Resynchronizing the M24xxx s internal logic If the Bus Master (the microcontroller or processor) or other components on the I²C bus have failed, with clock and data lines being improperly driven, the internal state of the M24xxx might reach an unknown state. The M24xxx internal logic must be resynchronized. The analysis of this situation can be structured under the following sub-headings: The interrupted transmission was an Incoming data Byte The interrupted transmission was an Outgoing data Byte (during a READ cycle) 1.1 The interrupted transmission was an Incoming data Byte The issue of a STOP condition is sufficient to abort the transmission. However, if the last transmitted instruction was a WRITE, the STOP condition is also able to start the internal Write cycle (if the STOP condition occurs after the 9th clock cycle of each data Byte). It is therefore risky to send a single STOP condition. It is recommended, instead, to issue a START condition first, followed by a STOP condition. The START condition aborts the transmission, and leaves the M24xxx waiting for a Device Select Code; the STOP condition then sets the M24xxx in stand-by mode. Caution: resynchronization does not modify the internal address counter.In order to define the internal address counter value, the next instruction must be Byte Random Read, Sequential Random Read or Write (the current Read or Sequential Read instruction does not modify the internal address counter). August 2006 Rev 3 1/4 www.st.com Resynchronizing the M24xxx s internal logic AN1471 - Application note 1.2 The interrupted transmission was an Outgoing data Byte (during a READ cycle) A tricky configuration might be reached if, after loosing the Bus communication control, the M24xxx memory is stopped when outputting a "0" on SDA. In such a case, even if the Bus Master transmits a START condition, the M24xxx memory cannot decode it as the "SDA bus" is forced to "0". A good way to work around this state is to have the Bus Master sending several clock cycles until the M24xxx outputs a "1": once the "1" state has been output, a START condition transmitted by the Bus Master will be correctly decoded by the M24xxx memory. The same result can be reached using a blind sequence, with two possible outcomes: a) worst case: when it lost the Bus communication control, the M24xxx memory device was starting to clock out eight 0s (the data Byte was 00h), as shown in Figure 1.As the ninth clock pulse makes the M24xxx output a NoAck state ("SDAout from memory device" is "1"), the falling edge of "SDAout from Bus Master" correctly drives the "SDAbus" and this event is decoded as a START condition by the M24xxx memory. b) standard case: when it lost the Bus communication control, the M24xxx memory device was starting to clock out a Byte composed of "0s" and "1s"; the START condition is decoded sooner, that is with the first bit of data "SDAout from Memory Device" ="1". In such a case, the M24xxx memory decodes N successive START conditions (one START condition for each "SDAout from Memory Device" ="1") which restart the M24xxx memory N times, before decoding the final STOP condition (see Figure 1). Caution: resynchronization does not modify the internal address counter.In order to define the internal address counter value, the next instruction must be Byte Random Read, Sequential Random Read or Write (the current Read or Sequential Read instruction does not modify the internal address counter). Figure 1. Nine attempts at a START condition and then a STOP condition 1 2 3 4 5 6 7 8 9 SCL from Bus Master SDAout from Bus Master


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